In general, an IC test system performs an IC device test by electrically contacting IC devices to be tested with test contactors in pin electronics or pin cards provided in a test head area to supply test signals to the IC devices and receive the resulted outputs from the IC devices. The resulted signals are compared with expected signals to determine whether the outputs from the IC devices are acceptable or not.
Hence, an automatic handler transfers IC devices to be tested from a supply area to a test head area. After the test, IC devices that have been tested are transferred from test the head area to a discharge area and are sorted according to the test results. During these times required for transferring the IC devices, the test cannot be performed since IC devices to be tested cannot determine their position with respect to contactors in the test head and thus they cannot be electrically contacted. Reducing this transfer time, i.e., an index time, is desirable since the index time is useless for the IC device testing. Hence, there is a need to minimize the index time in an automatic handler.
FIG. 7 shows a conventional automatic handler for an IC test system. As shown, test trays 20 are used as means of transferring IC devices 16 to be tested in the IC test system. A plurality of carrier modules 30 are maintained in a floating state in each test tray 20. An IC device 16 is mounted on each carrier module 30. The test trays 20 having the IC devices 16 are arranged at the supply area SU. IC devices 16 are then transferred to the test head area TH while being maintained on the test tray 20. At the test head area TH, the test tray 20 is carried on a belt conveyer 18 by a driving power of a motor 17 until the test tray is stopped by a projection of a stopper 11.
At the test head area TH, the test tray 20 is positioned and fixed by the stopper 11. Then, the IC devices 16 are pushed downward, for example, for the electric connection with the test contactors of the pin electronics (not shown) provided at the test head in the IC test system. The IC devices 16 keep electronic contact with the pin electronics in the IC test system during the testing. Recently, a plurality of test head areas are provided for performing simultaneous testing of IC devices mounted on a plurality of test trays. The test tray 20 is then transferred to the discharge area DI where the IC devices 16 are classified depending on the test results.
FIG. 8 is a schematic diagram showing an example of test process in a conventional automatic handler. In the example shown in FIG. 8A, there are four (4) IC devices 16 seated in the test tray 20. In recent years, smaller devices are widely used and thus a larger number of IC devices, such as eight (8) IC devices can be arranged in the test tray 20 according to the actual density of IC devices as shown in FIG. 8A. However, a distance between the IC devices is limited to x in FIG. 8A because of the limitation in a packaging density such as in the contactors of the pin electronics in the test heads. Namely, since the test contactors in the pin electronics of the IC test system consist of mechanical and electronics parts and thus require a certain size and space which determines the minimum distance x.
Hence, in the example of FIG. 8A, four IC devices 16 are arranged in a length L of the test tray 20. The test tray 20 is shifted from the supply area SU to the test head area TH. After the test tray 20 is transferred to the stopper 11 in the test head area TH, each IC device 16 is electrically contacted by the pin electronics (not shown) as shown in FIG. 8B and the test is initiated. After the test, the projection of the stopper 11 withdraws so that the test tray 20 transfers to the discharge area DI. As a result, the test for the IC devices in the next test tray can be ready. In the above procedure, when the transfer speed of the test tray 20 is s, the index time per device is expressed EQU t1=L/4s.
Since the IC test system of FIG. 8 has one test head, the index time per device per automatic handler is also EQU t01=L/4s.
FIG. 9 is a schematic diagram showing an example of test process of IC device testing in another conventional automatic handler. In the example of FIG. 9, the IC test system includes two test heads TH1 and TH2. As shown in FIG. 9, eight (8) IC devices 16 are arranged in the test tray 20. The spacings between the IC devices to be tested are y where it is assumed that x/2&lt;y&lt;x. The IC devices 16 to be tested are arranged in the way that the spacing y between the IC devices 16 to be tested are minimized to the limit of the packaging density of the IC devices 16 in the length L of the test tray 20. In contrast, as discussed above with reference to FIG. 8, the distance x is determined by the density of the test contactors in the pin electronics which is larger than that of the IC devices.
As shown in FIG. 9A, the test tray 20 is transferred from the supply area SU to the first test head TH1 by the transfer system such as shown in FIG. 7. The position of the test tray is determined by the stopper 11.sub.1 provided at the first test head TH1 by the transfer system. Then, the IC devices 16 on the test tray are electrically contacted with the pin electronics in the test head area so that the test is initiated. Since there is a limitation in the density such as in the pin electronics or pin cards in the test heads, and thus the plurality of test contactors in the pin electronics have a greater spacing x than the spacing y of the IC devices 16 to be tested, not all IC devices 16 in the test tray 20 can be simultaneously tested. Therefore, for example, at the first test head TH1, only the IC devices 16 of odd lines in the test tray 20 are electrically contacted and tested. This is shown in FIG. 9B by the shades of the corresponding IC devices 16 in the test tray 20.
After finishing the test for the IC devices 16 in the odd lines, the projection of the stopper 11.sub.1 at the test head TH1 is detracted and the test tray 20 is transferred to the second test head TH2 as shown in FIG. 9C. The test tray 20 is positioned accurately at the second test head TH2 by the stopper 11.sub.2. At the test head area TH2, this time, only the IC devices 16 of even lines in the test tray 20 are electrically contacted by the pin electronics in the second test head TH2 as shown by the shaded lines in FIG. 9C.
Since there are two (2) test heads TH1 and TH2 are provided in this example and both test heads can perform the test simultaneously, it is possible for the second test head TH2 to test the IC devices in the even lines in the test tray 20 while the first test head TH1 simultaneously tests IC devices in the odd lines in the next test tray. Thus, all eight (8) IC devices 16 to be tested in the test tray 20 can be tested in the manner described above by allocating the IC devices to the first test head TH1 and the second test head TH2. After the test, the projection of the stopper 11.sub.2 at the second test head TH2 pulls back, and the test tray 20 is transferred to the discharge area DI as shown in FIG. 9D.
In this situation, when the transfer speed of the test tray 29 is expressed as s, the index time per device in the simultaneous testing performed continuously as above is: EQU t2=L/8s.
The index time per device per automatic handler is: EQU t02=L/4s.
As shown above, the index time per automatic handler needs L/4s for either t01 or t02 cases. Hence, whichever conventional means of FIGS. 7 or 9 are performed, the time length for the transfer of the test tray is limited to the index time above and cannot be decreased any further.